delay lock loop造句
例句與造句
- Firstly , the principle and realization of the step acquisition and delay locked loop are discussed
首先，論文討論了步進捕獲延遲鎖定環(huán)的原理及實現(xiàn)機理。 - The principle of large step fast acquisition and the circuit design of large step fast acquisition delay lock loop ( lsdll ) are disgussed as the emphasis
本文著重從理論和電路設(shè)計兩方面對大步進快速捕獲方法和大步進快速捕獲延遲鎖定環(huán)進行討論。 - In the second part , some of the multipath mitigation techniques widely used presently are analysed and compared with each other , from which we select the medll ( multipath estimating delay lock loop ) technique as the multipath mitigation algorithm in scope of signal processing in the receivers
第二部分通過對目前常用的多徑消除技術(shù)進行分析與比較,選擇了medll技術(shù)作為接收機信號處理階段的多徑消除算法。 - There are two uncertain factor about it : the phase of the pn code and the doppler - shift . after capturing the received signal successfully , the traditional ds receiver always uses a delay locked loop ( dll ) to synchronize the pn code and then uses a costas loop to realize the carrier synchronization . this complex closed - loop structure not only take long time to realize the synchronization , but also has the defect of “ hang up ”
傳統(tǒng)的擴頻接收機通常在捕獲偽碼信號后利用遲早門鑒相的延時鎖定環(huán)來實現(xiàn)偽碼的精同步,解擴后利用科斯塔斯環(huán)實現(xiàn)載波同步,這種閉環(huán)結(jié)構(gòu)不僅同步時間長、結(jié)構(gòu)復(fù)雜,而且鎖相環(huán)還存在所謂的“ hang - up ”現(xiàn)象。 - Chapter one introduces the recent development of usb2 . 0 and the overall architecture of transceiver interface ; chapter two proposes the design flow and design style ; chapter three presents the whole system and module partition ; chapter four emphasizes on the dual - mode transmitter circuit , and gives out the simulation waveforms ; chapter five focuses on the design of over - sampling receiver and dll ( delay locked loop ) module ; chapter six designs the band - gap reference circuit . in the end , it concludes the design , and estimates the trend of usb . the dissertation is emphasized on dual - mode transmitter architecture , implementation of high speed dll using dba ( digital - based analog ) technology and a new design methodology for complex digital modules in mixed - signal circuit
本文第一章介紹了usb2 . 0的發(fā)展現(xiàn)狀和收發(fā)器接口芯片系統(tǒng)；第二章介紹了該芯片的設(shè)計流程和風(fēng)格；第三章介紹了該接口芯片的總體構(gòu)架以及模塊劃分；第四章著重介紹雙模發(fā)送器電路設(shè)計并給出了仿真驗證波形；接下來第五章分析了過采樣接收器的設(shè)計并對其中的dll ( delaylockedloop )模塊設(shè)計進行了詳細的分析；第六章介紹了本芯片內(nèi)置的基準(zhǔn)電壓源的設(shè)計；最后對本文的設(shè)計一個總的回顧和總結(jié)，并展望下一代usb的發(fā)展方向。 - It's difficult to find delay lock loop in a sentence. 用delay lock loop造句挺難的
- By complementing the proposed scheme with methods to estimate the fractional code delay , the acquisition unit an provide high quality delay estimates such that it can instead of the delay locked loop in the traditional ds receiver . after dispreading successfully , this dissertation introduces a method to estimate the doppler - shift directly from some samples based maximum likelihood estimation , and then revise it forwardly
在成功解擴之后,本文利用最大似然估計從l個樣點中直接估計出殘余多普勒頻偏,并進行前向頻偏校正,來代替?zhèn)鹘y(tǒng)擴頻接收機中的科斯塔斯環(huán),經(jīng)仿真證明該方法的估計精度完全滿足解調(diào)的要求。 - The clock recovery block of usb2 . 0 transceiver macrocell consists of phase locked circuit , such as pll and dll ( delay locked loop ) . this block use external crystal 12mhz sin signal to produce 60mhz , 120mhz , 480mhz clock signal , and can recover colock signal form date wave . it can support 480mbps ( hs ) and 12mbps ( fs ) word speeds as defined in usb2 . 0 specification .
目的是用鎖相環(huán)電路? pll和dll (延遲鎖相環(huán))實現(xiàn)usb2 . 0收發(fā)器宏單元utm的時鐘恢復(fù)模塊。其中pll環(huán)路構(gòu)成的時鐘發(fā)生器將外部晶振的12mhz正弦信號生成60mhz 、 120mhz 、 480mhz等本地時鐘信號。 dll環(huán)路依據(jù)本地時鐘信號對外部數(shù)據(jù)信號進行時鐘恢復(fù)。 - It consists of three main parts : in the first part , we analyse the effect of multipath on code - tracking loops of receivers in spread - spectrum ranging systems . first , we establish the model of received signals with the present of multipath through the presentation of multipath ’ s characters . then , we analyse the theory of delay lock loop ( dll ) , based on which we derive the tracking error of dll caused by multipath
首先通過對多徑信號特性的分析得到存在多徑時的接收信號模型,然后在對擴頻測距系統(tǒng)的延遲鎖定環(huán)路( delaylockloop )工作原理的分析的基礎(chǔ)上,闡明了多徑存在時碼跟蹤環(huán)路產(chǎn)生誤差的機理。